Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate In order to provide a basis for comparison, we also analyze a NAND gate and half-adder circuit implemented in complementary metal oxide semiconductor technology to show how the fundamental bound of the Brownian circuit compares against a conventional paradigm. The method we employed here establishes a solid ground that enables studying computational and physical features of this emerging technology on an equal footing, and yield fundamental lower bounds that provide valuable insights into how far its efficiency can be improved in principle. In this paper, we perform a physical-information-theoretic analysis on the efficiency limitations in a Brownian NAND and half-adder circuits implemented using SET technology. One of the potential realizations of such circuits is via single electron tunneling (SET) devices since SET technology enable simulation of noise and fluctuations in a fashion similar to Brownian search. A Brownian cellular automaton, where signals propagate randomly and are driven by local transition rules, can be made computationally universal by embedding arbitrary asynchronous circuits on it. Brownian circuits are among the promising alternatives that can exploit fluctuations to increase the efficiency of information processing in nanocomputing. The saturation in the efficiency and performance scaling of conventional electronic technologies brings about the development of novel computational paradigms. Preliminary findings from a physical-information-theoretic methodology The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.įundamental energy limits of SET-based Brownian NAND and half-adder circuits. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. Then a 2-input NAND gate was modeled similar to the inverter circuit. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. ![]() A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The inverter circuit was modeled similar to a standard CMOS inverter. ![]() The first step in forming a NAND gate is to develop an inverter circuit. The NAND gate is one of the fundamental building blocks of digital electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. Ho, Fat DuenĬonsiderable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |